Verification Engineer

Senior Verification Engineer (DDR5 / PMIC / CXL)
📍 Johns Creek, GA (Hybrid/Onsite)

About the Opportunity
Our client, a growing semiconductor organization, has recently expanded its U.S. footprint in the Atlanta area. This is a unique opportunity to join a high-performing engineering team focused on next-generation memory and interconnect solutions supporting data center and cloud infrastructure.
The role offers strong ownership, hands-on technical impact, and meaningful growth within a collaborative global environment.

Role Overview
We are seeking an experienced Verification Engineer to design and develop system-level UVM testbenches for advanced memory and interconnect products, including DDR5 DIMMs, Power Management ICs (PMIC), and CXL-based solutions.
This individual will play a key role in building verification infrastructure, driving system and IP validation, and collaborating across global engineering teams.

Key Responsibilities

Develop and implement UVM/SystemVerilog testbenches for system-level and IP verification
Build verification infrastructure, including stimulus, coverage models, assertions, and scripts
Perform functional verification for memory subsystem and mixed-signal components
Collaborate with design, product, and specification engineering teams
Partner with global verification teams across multiple sites
Debug failing simulations and regression issues
Participate in silicon debug and bring-up activities as needed
Mentor and guide junior engineers

Required Qualifications

BS or MS in Electrical Engineering, Computer Engineering, or related field
5+ years of verification experience in semiconductor environments
Strong hands-on experience building UVM testbenches from scratch
Proficiency with tools such as VCS, Xcelium, Verdi, or similar
Experience with mixed-signal or digital verification methodologies
Solid debugging and problem-solving skills

Preferred Qualifications

Knowledge of DDR5 protocol and/or CXL 2.0 specification
Experience with PMIC or memory subsystem verification
Familiarity with CMOS circuit design fundamentals

Why This Role

Work on cutting-edge memory and interconnect technologies
High visibility and ownership within engineering programs
Collaborative, global team environment
Strong opportunity for career advancement